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2023 Research Review

Co-Design for Edge AI: Application-Specific System on Chip


Hardware inefficiencies pose major limitations to U.S. Department of Defense (DoD) applications; current processors simply cannot keep up with the large and complex machine learning (ML) workloads needed to perform their missions. Utilizing co-design (concurrent design of electronic system hardware and software components), this project aims to provide tools to overcome these limitations and yield practical results that increase battery life, reduce weight warfighters must carry, increase maneuverability of forces, and reduce time from sensor to shooter.

This three-year project will develop accelerator intellectual property (IP) for novel ML accelerators that can be incorporated into specialized edge hardware that is optimized for mission size, weight, and power (SWaP). We will target the most computationally expensive parts of the application domain and focus on identifying accelerators for the ML workloads that are the primary performance bottlenecks in our target application systems. Our primary technical objective is to deliver application-dependent accelerator co-designs that are 2x more energy efficient than existing GPU solutions.

This project responds to a DoD need and opportunity to not only improve efficiency in targeted edge applications, but to do so at scale.

Dr. John Wohlbier
Senior Research Scientist and Lab Lead
Dr. John Wohlbier

Through analysis and simulation phases, our project will establish tools and methodologies for the identification and implementation of accelerators that will be incorporated into a co-design flow for system on chips (SoCs). Improving efficiency in edge applications is a challenging problem that involves simulations of the integrated system, as well as simulations of the newly designed component and how it integrates into the system. This project responds to a DoD need and opportunity to not only improve efficiency in targeted edge applications, but to do so at scale.

Advancing the capability of hardware-software co-design will result in improvements in energy efficiency that improve timeliness and affordability by saving time and resources. Because leading-edge software capabilities are foundational to this work, the CMU SEI is uniquely suited to lead this project and set a course for hardware-software co-design for the DoD.

Co-Design Flow for System on Chips Co-Design Flow for System on Chips


In Context: This FY2023-25 Project

  • is a collaborative effort utilizing researchers from the CMU SEI, Carnegie Mellon University, and DARPA and building on previous knowledge from the CMU SEI’s projects related to automated code generation and ML algorithm execution on ultra-low power devices
  • leverages the CMU SEI’s expertise and experience in low-level hardware, performance engineering, software development, developing and characterizing the performance of ML and AI algorithms, and using the latest hardware and software co-design tools
  • aligns with the CMU SEI technical objective to bring capabilities that make new missions possible or improve the likelihood of success of existing ones
  • aligns with the OUSD(R&E) critical technology priorities, of leveraging advanced computing and software, building trusted AI and autonomy, developing integrated sensing and cyber technology to counter advanced threats, and creating defense microelectronic solutions