Complex, cyber-physical DoD systems, such as aircraft, depend on correct timing to properly and reliably execute crucial sensing, computing, and actuation functions. Any timing failure can have disastrous consequences--an expected delay translating sensor data into actuation can cause system instability and loss of control. What’s more, the complexity of today’s DoD systems has increased the demand for use of multicore processors because unicore chips are either unavailable or not up to the task. However, concerns about timing have led to the practice of disabling all processor cores except one.

In this project, we aim to develop a solution to overcome this obstacle. This is a difficult challenge, because timing is determined by many shared resources in the memory system (including cache, memory banks, memory bus) with complex arbitration mechanisms, some of which are undocumented. The goal of our research is to demonstrate multicore timing confidence by achieving the following sub-objectives:

• Verification. Develop a method for timing verification that does not depend directly on undocumented design qualities and quantities.
• Parameter extraction. Develop a method for obtaining values for parameters in the model of a software system suited for the timing verification procedure mentioned above.
• Configuration. Develop a configuration procedure (such as assigning threads to processor cores or assigning priorities to threads) that takes a model as input and produces a configuration for which the verification will succeed (if such a configuration exists).